As the size of CMOS devices is reduced into the submicron region, the operating frequency of an output driver increases to frequencies of 60 Mhz and higher, reducing rise/fall times and the pulse width of output signals. For a device utilizing a 5 volt supply, an output driver operating frequency of 60 MHz corresponds to an output transient time less than 0.4 V/ns for a given load capacitance (i.e. T.sub.r =T.sub.f &lt;7 ns for C.sub.Load =25 pF). An increase in switching speed of an output buffer increases the rate of change of switching current which, in combination with chip-package interface power distribution parasitics, creates ground bounce and electromagnetic interference (EMI) noise when output drivers switch simultaneously. It is essential that an output driver limit ground bounce and EMI noise to within a maximum allowable noise level. Otherwise unreliable operation, such as false triggering, double clocking, missing clock pulses and the like, occurs in logic devices that are connected to the same supply and ground reference lines. Various governmental regulations, for example FCC regulations, set a standard maximum electromagnetic interference (EMI) level. Devices and systems emitting too large an EMI level fail these standards and cannot be sold.
Various output driver design methodologies have been practiced in application-specific integrated circuits (ASICs) to attempt to solve the problems of EMI emissions and ground bounce. These methodologies are implemented, for example, in a current-controlled output driver, a controlled-slew rate output driver and a slow ramp high drive output driver.
FIG. 1, labelled PRIOR ART, illustrates a conventional CMOS output driver 100 in which the gate input terminals of a final stage p-channel transistor 102 and a final stage n-channel transistor 104 are tied together so that through current I.sub.T, the component of output driver current flowing directly from supply to ground, is not minimized. Through current I.sub.T does not contribute to charging or discharging of the load capacitance C.sub.LOAD, but rather simply contributes to the switching noise of the output driver. The current pulse in this buffer has a very sharp rise time. The current during switching rises from zero to a maximum current in less than 2 ns.
FIG. 2, labelled PRIOR ART, illustrates a known current-controlled output driver 200 which reduces noise by controlling the maximum switching current I.sub.max of the switching output signal. However, controlling the maximum switching current also disadvantageously limits the switching speed of the output driver. The switching speed of a fully current-controlled output driver is always less than or equal to the switching speed of an equivalent current unregulated output driver. Another disadvantage of the current-controlled output driver 200 is that both the "push" and complementary "pull" portions of the final stage of the output driver 200 include two drive transistors so that a larger circuit area is required for the driver. Furthermore, the current pulse generated by the current-controlled output driver 200 does not optimally avoid EMI emissions and ground bounce.
FIG. 3, labelled PRIOR ART, illustrates a known controlled slew rate output driver 300 which reduces noise by controlling switching output signal rise and fall times. The current pulse generated by the controlled slew rate output driver 300 does not optimally avoid EMI emissions and ground bounce.
FIG. 4, labelled PRIOR ART, depicts a known slow ramp high drive output driver 400 as described in U.S. Pat. No. 5,111,064, "Slow Ramp High Drive Output Pad" to James Ward, issued May 5, 1992. A CMOS drive circuit in an integrated circuit bonding pad is controlled by a pre-driver signal to change the potential on the output pad in accordance with these signals. Undesirable interference (EMI) problems are eliminated or significantly reduced by slowing the ramp of change of the signal appearing on the output bonding pad when it changes from a high or positive binary state to a lower, relatively negative binary state. This is affected by splitting the output NMOS transistor of the CMOS output driver into two parallel connected, relatively small-sized transistors. Each of these transistors is driven from the signal input terminal through a relatively low current source which causes the gate capacitance to be slowly charged. Circuit 400 disadvantageously slows the output signal. Furthermore, the current pulse generated by the slow ramp high drive output circuit 400 does not optimally avoid EMI emissions and ground bounce.